Álvaro Silva, a Ph.D. candidate at FEUP in Portugal, aspires to research the interconnection between Formal Verification and generative AI applications. Previously, Álvaro was an ASIC Digital Design Staff Engineer at Synopsys, where he performed functional and formal digital IP verification for automotive-grade products. In this role, Álvaro gained an appreciation for software verification and the challenges it presents. He holds an integrated Master’s degree in Electrical and Computer Engineering from FEUP, where he graduated with a GPA of 19/20. Recognized for his academic excellence, Álvaro was awarded two merit scholarships.
I am an Early Stage Researcher at the ARSR group in INESC-ID. I concluded my BSc. and MSc. at Instituto Superior Técnico. Recently I have been researching Program Synthesis applied to the synthesis of SQL queries, and how we can make sure to satisfy the user’s true intent.
Since my Master’s Thesis, I have been researching program synthesis, the task of constructing a computer program based on a high-level description of what it should do. I will continue to explore this topic on my PhD: through program synthesis, I hope to find ways to help everyone easily and safely use a computer to automate daily tasks.
I am PhD Student in the School of Computer Science at Carnegie Mellon University. Broadly, my research goal is to create methods and tools to help software developers by automating tedious (but necessary) refactoring tasks. Currently, my primary focus is on automatic library migration and transpiration, but I have also worked on program synthesis.
